Various types of semiconductor memory exist. One type of volatile semiconductor memory is Static Random Access Memory (SRAM). SRAM modules, and their memory cells, have become very small. The small size of the cells has led to stability issues.
One such stability issue is read failures caused by high supply voltages (Vdd). FIG. 1 is an illustration of system 100, which includes a conventional memory cell having a bit line BL, a complementary bit line BL_, a wordline WL, and transistors T1, T2, T3, T4, T5, T6. In this example, system 100 stores a value of 0 at node NL and a value of 1 at node NR.
Prior to a read operation, the bit lines BL, BL_ are precharged to a supply voltage Vdd. During the read operation, the word line (WL) turns on and the voltage at node NL rises. The increase is an amount based upon a ratio between the transistors T5 and T2 and the supply voltage Vdd (due to channel resistance of the transistors T5 and T2). If the supply voltage Vdd is too high, the voltage at node NL surpasses the trip point of the T3, T4 inverter, the latch loses its state, and a read failure occurs.
It is known that read stability can be enhanced by decreasing the precharge voltage applied to the bit lines prior to accessing the bit cell (i.e. enabling the wordline WL). However, a challenge is how to reduce the precharge voltage.
FIG. 2 is graph showing an example illustration of failure rate versus precharge voltage drop (ΔV) for a conventional memory cell, such as that of system 100 of FIG. 1. FIG. 2 shows that as the precharge voltage is dropped (i.e., as ΔV gets bigger), the failure rate decreases and then increases again. Point 201 shows the precharge voltage drop with the highest stability (and highest Static Noise Margin (SNM)) in this example.
One particular prior art solution proposes using a voltage regulator circuit to lower the precharge voltage from Vdd. However, voltage regulator circuits are complex and expensive. Another solution proposes a diode drop for reducing the precharge voltage from Vdd. However, a diode drop will reduce the voltage by too much, increasing the failure rate.
Another proposed solution includes using two power supplies for the memory—one for the bit cell and one for the periphery. Complexity is added, however, because the voltage difference between the two power supplies requires strict limitation due to possible SNM degradation when the difference gets too high. Also, the limitation on the voltage level differences establishes a limit on the power savings that can be achieved by reducing the voltage of the periphery power supply.
The prior art provides no low-cost and simple solution for decreasing bit line precharge voltages to reduce read failures.